1. Field of the Invention
The present invention relates to an apparatus and method for forming isolation structures for isolating electrical devices on a semiconductor substrate. More particularly, the present invention relates to forming the isolation structure using a novel LOCOS (LOCal Oxidation of Silicon) technique.
2. State of the Art
The fabrication of an electrical circuit involves connecting isolated electrical devices with specific electrical paths. For the sake of example only, the follow discussion will focus on the formation of a twin-well CMOS (Complementary Metal Oxide Semiconductor) structure. In the fabrication of a CMOS integrated circuit, the isolation structure for electrically isolating the electrical devices must be built onto or into the silicon wafer itself. The individual electrical devices are generally isolated using the LOCOS process. FIGS. 14 through 27 illustrate the LOCOS process which begins with a semiconductor substrate 202, such as a silicon wafer, having p-wells 204 and n-wells 206 formed thereon, as shown in FIG. 14. A layer of silicon dioxide 210, usually between about 20 and 50 nm thick is formed on an active surface 208 of the semiconductor substrate 202, as shown in FIG. 15. The silicon dioxide layer 210 may be formed by any known technique, including but not limited to: thermally growing the layer, CVD (chemical vapor deposition), and the like. The function of the silicon dioxide layer 210, also called pad or buffer oxide, is to lessen the stresses between the semiconductor substrate 202 and a subsequently deposited silicon nitride layer.
As shown in FIG. 16, after the formation of the silicon dioxide layer 210, a thick layer of silicon nitride 212, usually between about 100 and 200 nm thick, is deposited, generally by CVD, over the silicon dioxide layer 210 to function as an oxidation mask. Active areas are then defined with photolithographic and etch steps illustrated in FIGS. 17 through 23.
As shown in FIG. 17, a resist layer 214 is patterned on the silicon nitride layer 212 to protect all of the areas where active areas will be formed. The silicon nitride layer 212 is etched, usually by a dry etch, and the silicon dioxide layer 210 is then etched, usually with either a dry or wet etch, as shown in FIG. 18. FIG. 19 illustrates a top view of an exemplary resist layer pattern 220. As shown in FIG. 20, the resist layer 214 is removed and the isolation structure or field oxide 216 is then formed, usually thermally grown by wet oxidation at temperatures of about 1000.degree. C. for between about 2 and 4 hours. As the field oxide 216 grows, some of the oxidation diffuses laterally which causes the field oxide 216 to grow under and lift edges 218 of the silicon nitride layer 212. FIG. 21 illustrates a top view of FIG. 20. The silicon dioxide layer 210 is shown in dashed lines for visual orientation. Area 222 is shown with a silicon nitride layer 212 removed (dashed line showing previous location) to show the encroachment of the field oxide 216. The field oxide 216 encroaches in direction 224 and, simultaneously, in direction 226. This encroachment will ultimately reduce the size of an active area to be formed (see FIG. 23). In fact, a resulting active area length can shrink severely (about &gt;0.11 .mu.m per side for an active area having a beginning length of about 1.5 .mu.m) due to the encroachment. However, the shrinkage of a width of the active area is less sensitive. The active area width usually reduces only slightly (&lt;0.04 .mu.m per side for an active area having a beginning width of about 0.3 .mu.m).
The silicon nitride layer 212 is then removed to expose the silicon dioxide layer 210, as shown in FIG. 22. The field dioxide 216 and silicon dioxide layer 210 are etched to remove the silicon dioxide layer 210 and expose the active areas 230 on the p-wells 204 and n-wells 206, as shown in FIG. 23.
The active areas 230 are then used to form individual electrical devices, such as PMOS, NMOS, and CMOS transistors. For purposes of illustration, FIGS. 24 through 27 show the formation of semiconductor-layer source and drain regions for a CMOS transistor. The source and drain regions are formed by introducing an impurity element into the semiconductor layer (see U.S. Pat. No. 5,514,879 issued May 7, 1996 to Yamazaki). Typically, the introduction of impurities for a CMOS transistor requires two masking and implantation steps. As shown in FIG. 24, spacers 232 are used to substantially bifurcate the active areas 230. As shown in FIG. 25, a first mask 234 is applied over the active areas 230 over the n-wells 206. An n-type impurity is introduced to the exposed active areas 230 over the p-wells 204 to form n-type areas 236. The first mask 234 is removed and a second mask 238 is applied to the active areas 230 over the p-wells 204, as shown in FIG. 26. A p-type impurity is introduced to the exposed active areas 230 over the n-wells 206 to form p-type area 240. The second mask 238 then is removed to form the fundamental CMOS structure 242, as shown in FIG. 27. The n-type areas 236 and the p-type areas 240 are subsequently used as source/drain areas in further CMOS fabrication.
The p-type and n-type impurities can be introduced by thermal diffusion or ion implantation. By using thermal diffusion, the impurities are introduced from the surface of the semiconductor layer. By using ion implantation, impurity ions are implanted into the semiconductor layer. The ion implantation method provides a more precise control with respect to the total impurity concentration and depth that the impurities can be implanted into the semiconductor layer, and thus allows impurities to be implanted into a shallow, thin film. However, since an ion implantation apparatus uses an ion beam having a diameter of only several millimeters, it is necessary to either move the substrate mechanically or scan the ion beam electrically over the substrate since the area of the substrate is larger than the diameter of the ion beam. Thus, an alternate technique is an ion shower-doping method. According to this technique, ions are generated by using a plasma discharge. The ions are dispersed in a cone shape and accelerated at a low voltage without mass separation to implant in the substrate.
Once the implantation is complete, the CMOS structure 242 is annealed at about 600.degree. C. to activate the impurities. However, the temperature of annealing is detrimental to any temperature-sensitive portion of the entire structure. Furthermore, it is known that any metal contamination in the furnace/holder will out-diffuse and contaminate the semiconductor wafers containing the CMOS structures 242 during the high temperature anneal. In order to eliminate this problem, a highly clean furnace and wafer holders are required. It is also known that any metal contamination in any individual semiconductor wafer will contaminate other nearby semiconductor wafers in the same batch during high temperature anneal.
Therefore, it would be advantageous to develop an electrical device isolation technique which substantially eliminates the aforementioned contamination effects and reduces encroachment of the field oxide into the active areas, while using inexpensive, commercially-available, widely-practiced semiconductor device fabrication techniques and apparatus.